The HMC855LC5 is a 1:4 demultiplexer designed for data deserialization applications up to 28 Gbps. The device uses the rising and falling edges of the half-rate clock to sample the input data sequences D0-D3 and latch the data to the differential output. An on-chip 1/4 rate clock output signal is generated that can be used to read data into other devices. The demultiplexer is DC-coupled and supports wideband operation.
All clock and data inputs of the HMC855LC5 are CML and terminated to the positive supply GND via an on-chip 50 Ω, either DC or AC coupled. The differential output is terminated to 50 Ω and can also be AC or DC coupled. The outputs can be connected directly to a 50-Ω ground-terminated system or via CML logic input drivers. The HMC855LC5 also integrates an output level control pin, VR, which can be used for loss compensation or signal level optimization. The HMC855LC5 operates from a single -3.3V supply and is available in a RoHS-compliant 5x5 mm SMT package.
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- SONET OC-192
- Broadband test and measurement
- Serial data transmission up to 28 Gbps
- FPGA interface