- 5-bit LVDS interface
- No external VCO or clock requirements are required
- Clock recovery serial loop-through with cable driver
- Power-down mode
- 3.3 SMBus configuration interface
- Small 48-pin LLP package
- Industrial temperature range: -40 °C to +85 °C
illustrate
The LMH0341/0041/0071/0051 SDI deserializer is part of National Semiconductor's FPGA-Connect SER/DES 5-bit LVDS interface product family with FPGAs. When paired with the host's FPGA the LMH0341 automatically detects the input data rate for any of the following standards and decodes the original 5-bit data word standard: DVB - ASI, SMPTE 259M, SMPTE 292M or SMPTE 424M. see For details, while standard is supported per device.
The interface between the LMH0341 and the host FPGA includes a 5-bit wide LVDS bus, LVDS clock and an SMBus interface. No external VCO or clock is required. The LMH0341 of the CDR detects the frequency of the input data from the stream, produces a clean clock and sends the clock and FPGA to the host data. While the LMH0341, LMH0041 and LMH0071 include an integrated SMPTE standard cable driver, serial clock recovery loop-through. Refer to Table 1 for a complete list of single-channel deserializers available in this family.
FPGA connectivity is supported by the SER/DES family of products, an IP suite that allows design engineers to quickly develop video applications using SER/DES products. The product is packaged in a small 48-pin LLP package.
Main specifications
- Output compatible with SMPTE 259M-C, SMPTE 292M, SMPTE 424M and DVB-ASI (see Table 1)
- Typical power consumption: 590 mW (loop-through disability, 3G data rate)
- 0.6 UI minimum input jitter tolerance
apply
- The SDI interfaces are:
- camera
- vcr
- Video switcher
- Video editing system
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