- Ultra-low RMS jitter performance
- 111 FS RMS jitter (12 kHz to 20 MHz)
- 123 FS RMS jitter (100 Hz to 20 MHz)
- Dual-loop PLLatinum PLL architecture
- PLL1
- Integrated low noise crystal oscillator circuit
- Hold mode when the input clock is lost
- Automatic or manual triggering/recovery
- PLL2
- -227 dBc/Hz noise floor attributed to the [1 Hz] PLL
- Phase detection rates are as high as 155 MHz
- OSCIN frequency multiplied
- Integrated low noise VCO
- 2 LOS extra input clock
- Automatic and manual switching modes
- 50% duty cycle output points, 1 to 1045 (odd and even)
- LVPECL, LVDS or LVCMOS programmable output
- Precision digital delay, fixed or dynamically adjustable
- 25 PS one-step analog delay control.
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14 differential outputs. Up to 26 single-ended.
- Up to 6 VCXO/crystal buffered output
- Up to 1536 MHz clock rate
- 0 delay mode
- The output power is up to the three default clocks
- Multi-mode: dual PLL, single PLL and clock distribution
- Industrial temperature range: -40 to 85 °C
- 3.15 V to 3.45 V operation
- Package: 64-pin LLP (9.0 × 9.0 × 0.8mm)
illustrate
The LMK04800 series is the industry's highest performance superior clock jitter removal, power generation, and distribution clock adjustment with advanced features to meet next-generation system requirements. The dual-cycle PLLatinum architecture enables 111 FS RMS jitter (12 kHz to 20 MHz) to use low-noise VCXO modules or low-cost external crystals and varactor diodes for 200 FS RMS jitter (12 kHz to 20 MHz).
The dual-cycle architecture consists of two high-performance phase-locked loops (PLLs), a low-noise crystal oscillator circuit, and a high-performance voltage-controlled oscillator (VCO). The first PLL (PLL1) provides the function of a low noise jitter cleaner, while the second PLL (PLL2) performs clock generation. The PLL1 can be configured to either integrate crystal oscillators with external VCXO modules or external tunable crystals and varactor diodes. When the loop bandwidth is narrow, PLL1 uses a VCXO block with upper stage phase noise or a tunable crystal to clean the proximity of the input clock (below 50 kHz offset). The output of PLL1 serves as an input reference, and PLL2 is cleanly locked with integrated VCO. The loop bandwidth of PLL2 can be optimized for use with clean phase noise (offset above 50 kHz) such as an integrated VCO block or a tuned crystal PLL1 superior to VCXO
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