- Four-synchronized A/V clocks generate PLLs
- PLL1: 27 or 13.5 MHz
- PLL2: 148.5 or 74.25 MHz
- PLL3: 148.5/1.001 or 74.25/1.001 MHz
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PLL4: 98.304 MHz/2 X (X = 0 to 15)
- 3 × 2 video clock intersection
- Flexible PLL bandwidth optimized jitter performance and lock time
- Soft resync to the new reference
- Digital deferred or free-running reference loss
- Missing reference and PLL out-of-lock status flags
- Single-supply 3.3V operation
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I 2 C interface and address selection pin (3 countries)
illustrate
The LMH1983 chip is a highly integrated, programmable audio/video (A/V) clock generator for broadcast and professional applications. It replaces multiple PLL and voltage control used in applications that support SMPTE Serial Digital Video (SDI) and Digital Audio AES3/EBU standards. It provides a low jitter reference clock for any SDI transmitter without the need for additional clock cleaning circuitry to meet stringent output jitter specifications.
The LMH1983 chip features automatic input format detection, multiple A/V output formats, genlock or digital free running mode, and programmable simple programming covering various automatic functions. Accepted input formats include HVF synchronization, 27 MHz, 10 MHz, 32/44.1/48/96 kHz audio word clocks for major video standards.
Two-stage PLL architecture with four phase-locked loops integrating three on-chip VCOs. The first stage (PLL1) uses an external low noise narrow loop bandwidth 27 MHz voltage controlled crystal oscillator to provide a clean reference clock for the next stage. The second phase (PLL2, 3, 4) consists of three parallel primary digital A/V clocks at the base rate, which includes a PLL of 148.5 MHz, 148.5/1.001 MHz and 98.304 MHz (4 x 24.576 MHz) simultaneously. Each PLL generates a clock and timing pulse indicator frame (TOF) at the top.
When the reference is locked, the internal 10-bit ADC tracks the loop filter control voltage. When the loss of reference (LOR) is made, the LMH1983 chip can be programmed to hold the control voltage to maintain an output accuracy of ± 0.5 ppm front reference (typical). The LMH1983 chip can be configured to resynchronize glitch operation with the previous reference.
The LMH1983 chip is available in a space-saving 6mm x 6mm 40-pin LLP package.
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- Three-speed (3G/HD/SD) SDI deserializer
- Reference clock generation/cleaning for FPGAs
- Audio embedding/de-embedding
- camera
- Frame synchronization (genlock, DARS)
- AD/DA converts, edits, processes cards
- Keyer and logo inserter
- Format/Standards Converter
- Video monitors and projectors
- A/V test and measurement equipment
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