AD9644BCPZ-155 14-bit, 80 MSPS/155 MSPS, 1.8V dual serial output ADC
The AD9644 is a 14-bit dual channelAnalog-to-digital converters(ADC) with a high speed serial output interface with a sampling speed of 80 MSPS or 155 MSPS.
The device is designed to provide a solution for high-performance, low-cost, small-size, versatile communications applications. The JESD204A high-speed serial interface reduces board routing requirements and reduces the number of pins required for the receiving device.
This dual ADC core uses a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features a wide bandwidth, differential sample-and-hold analog input amplifier that supports a variety of user-selectable input ranges. An integrated reference simplifies design. A duty cycle stabilizer can be used to compensate for fluctuations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.
By default, ADC output data is routed directly to two external JESD204A serial output ports, which are set to CML levels. The device supports two modes so that output encoded data can be sent over one or two data links. (L = 1; F = 4 or L = 2; F = 2) Each channel has an independent synchronization input (DSYNC).
Flexible power-down options can significantly reduce power consumption when needed.
Setup and control programming is accomplished using a 3-wire SPI-compatible serial interface.
The AD9644 is available in a 48-lead LFCSP package and is specified over the industrial temperature range of −40°C to +85°C.
This product is protected by a U.S. patent.
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-correspondence
- Diversity radio system
- Multi-mode digital receivers (3G and 4G)
GSM、EDGE、W-CDMA、LTE、
CDMA2000、WiMAX、TD-SCDMA
- I/Q demodulation system
- Smart antenna system
- Universal software radio
- Broadband data applications
- Ultrasound equipment
Product Focus
1. The on-chip PLL allows the user to provide a single ADC sampling clock, and the data rate clock is generated by multiplying the PLL by the ADC sampling clock.
2. When each ADC uses a dedicated data link, the configurable JESD204A output module supports data rates up to 1.6 Gbps per channel; When two ADCs share a data link, data rates can be as high as 3.2 Gbps.
3. The proprietary differential input maintains excellent signal-to-noise ratio (SNR) performance at input frequencies up to 250 MHz. 4. Operates from a single 1.8 V supply.
5. Standard serial port interface (SPI) supports various product features and functions, such as: data formatting (offset binary, twos complement or gray code), clock DCS enable, power saving mode, test mode, reference mode, and serial output configuration.