AD9644BCPZ-155 14-bit, 80 MSPS/155 MSPS, 1.8V dual-channel serial output ADC
The AD9644 is a 14-bit dual-channel analog-to-digital converter (ADC) with a high-speed serial output interface that can sample at 80 MSPS or 155 MSPS.
The device is designed to provide a solution for high-performance, low-cost, small-size, multi-function communication applications. JESD204A high-speed serial interface reduces board routing requirements and reduces the number of pins required for the receiver device.
This dual-channel ADC core adopts a multi-level, differential pipeline architecture and integrates output error correction logic. Each ADC features a wide-bandwidth, differential sample-holding analog input amplifier that supports a variety of user-selectable input ranges. Integrated voltage reference simplifies design. The duty cycle stabilizer can be used to compensate for fluctuations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.
By default, the ADC output data is routed directly to two external JESD204A serial output ports, which are set to CML levels. The device supports two modes to send output encoded data over one or two data links. (L = 1; F = 4 or L = 2; F = 2) Each channel has an independent synchronous input (DSYNC).
Flexible power-down options can significantly reduce power consumption when needed.
Programming of setup and control is done using a three-wire SPI-compatible serial interface.
The AD9644 is available in a 48-pin LFCSP package and is rated for an industrial temperature range of −40°C to +85°C.
The product is protected by a U.S. patent.
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-correspondence
- Diversity radio systems
- Multi-mode digital receivers (3G and 4G)
GSM、EDGE、W-CDMA、LTE、
CDMA2000、WiMAX、TD-SCDMA
- I/Q demodulation system
- Smart antenna system
- Universal Software Radio
- Broadband data applications
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1. The on-chip PLL allows the user to provide a single ADC sampling clock, which is generated by multiplying the PLL by that ADC sampling clock.
2. Configurable JESD204A output modules support data rates up to 1.6 Gbps per channel when each ADC uses a dedicated data link; When two ADCs share a data link, data rates can be up to 3.2 Gbps.
3. Proprietary differential inputs maintain excellent signal-to-noise ratio (SNR) performance at input frequencies up to 250 MHz. 4. Powered by a single 1.8 V power supply.
5. The standard serial port interface (SPI) supports various product features and functions, such as: data formatting (offset binary, binary complement or gray code), clock DCS enablement, power saving mode, test mode, reference voltage mode, and serial output configuration, etc.