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AD9869BCPZRL
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AD9869BCPZRL

  • Category:High-speed / wideband codec and analog front end High-speed logic
  • Product Name:Broadband modem mixed-signal front end
  • Manufacturers:Analog Devices
  • Production Batch Number:15+
  • Encapsulation:64 ld LFCSP
  • Stock Status:There is stock
  • Stock Quantity:980
  • Minimum order quantity: 1
  • Details:Click here to find pdf documentation for the AD9869BCPZRL
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  • Product introduction

Advantages and features

  • Low cost 3.3 V CMOS MxFE, fitBroadband modem
  • 12-bit digital-to-analog converter 
    2×/4× interpolation filter 
    200 MSPS DAC update rate
  • Integrated 17 dBm line driver with 19.5 dB gain control range
  • 12-bit, 80 MSPS analog-to-digital converter
  • Third-order programmable low-pass filter
  • −12 dB to +48 dB low noise RxPGA (
  • Flexible digital data path interface 
    Half-duplex and full-duplex operation
    Pin compatible with the AD9866
    Multiple shutdown/power-down modes
  • Internal clock multiplier (PLL)
  • 2 auxiliary programmable clock outputs
  • It is available in a 64-pin LFCSP_VQ package
  • Product details

    AD9869is a mixed-signal front-end (MxFE)® IC for transceiver applications requiring transmit path and receive path functionality at data rates up to 80 MSPS. The device is a low cost, pin-compatible version of the AD9866 that removes the current amplifier (IAMP) IOUTP function and limits the PLL VCO operating frequency range to 80 MHz to 200 MHz.


    The device is ideal for half- and full-duplex applications. The flexibility of this digital interface allows for simple interfacing with digital backends that support half- or full-duplex data transmission, so the AD9869 is often used to replace discrete ADC and DAC solutions. Power-down modes can reduce power consumption for individual function blocks or shut down unused modules in half-duplex applications. The serial port interface (SPI) allows software programming of many functional blocks. The on-chip PLL clock multiplier and synthesizer provide all required internal clocks, as well as external clocks for single crystal oscillators or clock sources.


    The transmit signal path consists of a 2×/4× low-pass interpolation filter, a 12-bit TxDAC, and line drivers. At an input data rate of 80 MSPS, the transmit path signal bandwidth can be as high as 34 MHz. The TxDAC provides a differential current output that can be directed directly to an external load or to an internal low distortion current amplifier (IAMP) capable of delivering 17 dBm peak signal power. The transmit power can be digitally controlled over a range of 19.5 dB in 0.5 dB steps.

    The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and a 12-bit ADC. The low-noise RxPGA has a programmable gain range of −12 dB to +48 dB in 1 dB steps; For gain settings above 36 dB, the input-referred noise is less than 3 nV/√Hz. The receive path LPF cutoff frequency can be set from 15 MHz to 35 MHz or simply bypassed. The 12-bit ADC achieves excellent dynamic performance up to 80 MSPS. Both the RxPGA and ADC provide adjustable power consumption for power/performance optimization.


    The AD9869 provides a highly integrated solution for many broadband modems. It is available in a space-saving 16-pin LFCSP package and is specified over the commercial temperature range of −40°C to +85°C.


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