- 100% software compatible with CLC5903
- In addition to the analog input and reference section the CLC5903 is pin-compatible
- DVGA of CLC5526 (123 dB dynamic range at 200kHz)
- Precision reference in the chip
- User-programmable AGC with enhanced power detector
- The channel filter consists of a 21-tap, 63-tap symmetrical flight information region followed by a fourth-order CIC
- Flexible output formats
- Serial and parallel output ports
- JTAG boundary scan
- 8-bit microprocessor interface
- 128-pin PQFP
illustrate
The LM97593 dual ADC/digital tuner/automatic gain control IC is a dual digital downconverter (DDC) that integrates a 12-bit analog-to-digital converter (ADC) and automatic gain control (AGC). The LM97593 further enhances the nation's receiver integration chipset with DDC wide bandwidth dual ADC core (DRCS). Includes one of the complete NDRC's LM97593 dual ADCs/digital tuners/AGCs and two CLC5526 digitally controlled variable gain amplifiers (DVGAs). The system directly samples the IF signal to enhance receiver performance and reduce system cost by 300MHz. One is shown in the block diagram of a DRCS-based narrowband communication system 。
The LM97593 provides high dynamic range digital tuning and filtering hardwired digital signal processing (DSP) technology based on it. Each channel has independent adjustments, phase offsets, filter coefficients, and gain settings. Channel filtering consists of a series of three filters. The first is a 4-stage cascaded integral comb (CIC) filter with programmable decimation ratios from 8 to 2048. This is followed by two symmetrical FIR filters, 21-tap, 63-tap, and two independent programmable coefficients. The first FIR filter extracts 2 data from the flight information region by 2 or 4 seconds. The channel filter bandwidth of 52MSPS ranges from ± 650kHz up and down ± 1.3kHz. At 65MSPS, the maximum bandwidth increase is ± 812kHz.
The AGC of the LM97593 controls the ADC output of the display and the input signal level of the ADC by adjusting the settings of the DVGA. AGC threshold, dead time + hysteresis, loop time constant are user defined. 123 dB is greater than the total dynamic range of the full-scale signal, and the noise at 200kHz bandwidth can reach the diversity of the receiver chip.
Main specifications
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Internal ADC resolution
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12 bits
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Sample rate
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65 MSPS
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Signal-to-noise ratio (= 11-bit F at 250MHz, Nyquist)
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62 dBFS (typical)
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SNR（fat= 200kHz at 250MHz)
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83 dBFS (typical)
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SFDR (F, 11-bit Nyquist at 250MHz)
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68 dBFS (typical)
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Full power bandwidth
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650 MHz (typical)
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Power Consumption (65MSPS)
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560 mW (typical)
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apply
- Cellular base stations
- GSM/GPRS/EDGE/GSM Phase 2 receiver
- Satellite receiver
- Wireless local loop receiver
- Digital
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