ADC08B200CIVSE

• Single-ended input
• The optional size of the capture buffer
• Phase-locked loop clock multiplier
• Refer to the top and bottom access of the ladder
• Linear power adjustment of the sample rate
• FPGA training mode
• Passed AEC - Q100 Level 2 qualified
• Power-down function

illustrate

ADC08B200 is a high-speed analog-to-digital converter (ADC) with an integrated capture buffer. The core of the 8-bit, 200 MSPS A/R&D is based on comprehensive tracking and proof of possession ADC08200 and optimized for low power consumption. The device includes a capture buffer that can be selectable up to 1,024 bytes in size, allowing fast input signals to be acquired and read out at a slower rate. An on-chip clock PLL circuit provides the option of on-chip clock rate multiplication to provide a high-speed sample clock.

The ADC08B200 is latch-up resistance and output short-circuit. ADC08B200 connection of the top and bottom of the reference ladder enables a wide range of input possibilities. A separate output supply pin supports a 2.7V to 3.3V logic interface and is a TTL/CMOS compatible digital output. The low voltage TTL/CMOS compatible output data format for digital inputs and outputs is binary.

ADC08B200Q runs in an automotive grade stream and passes AEC-Q100 Level 2 qualified.

ADC08B200 is available in a 48-pin plastic package (TQFP) specified to +105°C over the extended industrial temperature range of -40°C Evaluation boards provide assistance ADC08B200 are easy to evaluate.

Main specifications

(PLL bypass)

• power consumption

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• Laser ranging
• radar
• Pulse capture