ADC08B200CIVSE

• Single-ended input
• Optional size of the snap buffer
• Phase-locked loop clock frequency doubling
• Reference the top and bottom access of the ladder
• Linear power adjustment of the sample rate
• FPGA training mode
• Qualified by AEC - Q100 Class 2
• Power down function

illustrate

ADC08B200 is a high-speed analog-to-digital converter (ADC) with an integrated capture buffer. At the heart of the 8-bit, 200 MSPS A/R&D is based on synthetic trace and proof-of-holding ADC08200 and optimized for low power consumption. The device includes a selectable capture buffer of up to 1,024 bytes in size, allowing for slower acquisition and readout rates of fast input signals. A PLL circuit with an on-chip clock provides the option of on-chip clock rate multiplication to provide a high-speed sampling clock.

ADC08B200 is resistance to latching and output short circuits. ADC08B200 the connection of the top and bottom of the reference ladder enables a wide range of input possibilities. A separate output power pin supports 2.7V to 3.3V The logic interface is a TTL/CMOS compliant digital output. The low-voltage TTL/CMOS compatible output data format for digital inputs and outputs is binary.

ADC08B200Q runs in an automotive-grade stream and is AEC-Q100 Class 2 qualified.

ADC08B200 is to provide a 48-pin plastic package (TQFP) specified to +105°C for the extended industrial temperature range of -40°C The evaluation board provides assistance ADC08B200 is easy to evaluate.

Key specifications:

(PLR bypass)

• power consumption

apply

• Laser ranging
• radar
• Pulse capture