ADC08D1000WGFQV

• Internal sampling and holding
• Single +1.9 V ± 0.1 V operation
• Choice of SDR or DDR output clock
• Interleaved mode has a 2x sample rate
• Multiple ADC synchronization capability
• No code loss guaranteed
• Extended control of serial interfaces
• Fine-tune input full-scale and offset
• Duty cycle corrects the sampling clock

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ADC08D1000 is a dual-channel, low-power, high-performance CMOS analog-to-digital converter with 8-bit resolution and a maximum sampling rate of 1.3 GSPS for digital signals. From a single 1.9V power supply to 1 GSPS, a typical consumption of 1.6 watts, this device guarantees no loss of data throughout the entire operating temperature range. A unique folded interpolation architecture, a fully differential comparator design, internal sampling and retention amplifiers, and a self-calibration plan enable a very flat response. Innovative design for all dynamic parameters except Nyquist, producing a high ENOB 500 MHz input signal of 7.4 and a 1 GHz sampling rate, while delivering 10 -18 The BER output format is offset binary, with an adjustable common-mode voltage anomaly between 0.8V and 1.2V, and the LVDS digital output is IEEE 1596.3-1996 compliant.

Each converter has a 1:2 demultiplexer, feeds two LVDS buses, and reduces output data rates on each bus, with a sampling rate of half. The two converters can be interleaved and used as a single 2 GSPS ADC.

In power-down mode converters, the typical power consumption is less than 3.5 megawatts and 128 pins, enhancing the heat dissipation pad with exposed LQFP and operating in industrial environments (-40°C). ≤ T A ≤ 85°C) temperature range.

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• Direct RF downconversion
• Digital oscilloscope
• Satellite set-top box
• Communication system
• Test instruments