ADC08D1000WGFQV

• Internal sampling and holding
• Single +1.9 V ± 0.1 V operation
• Choice of SDR or DDR output clock
• Interleaved mode is 2x the sample rate
• Multiple ADC synchronization capabilities
• No missing codes are guaranteed
• Serial interface extended control
• Fine-tune input full-scale and offset
• Duty cycle correction sample clock

illustrate

The ADC08D1000 is a dual, low power, high performance CMOS analog-to-digital converter with 8-bit resolution and sampling rates up to 1.3 GSPS digitized signals. A typical consumption of 1.6 watts from a single 1.9 volt power supply at 1 GSPS, this device is guaranteed no missing codes over the entire operating temperature range. The unique folded interpolation architecture, the design of a fully differential comparator, the internal sample-and-hold amplifier and the self-calibration program enable an innovative design with a very flat response to all dynamic parameters other than Nyquist, producing an input signal with an ENOB of 500 MHz with a high 7.4 and a sample rate of 1 GHz while providing 10 -18 The BER output format is offset binary code, with an adjustable common-mode voltage anomaly between 0.8V and 1.2V, and the LVDS digital output is IEEE 1596.3-1996 compliant.

Each converter has a 1:2 demultiplexer, feeds two LVDS buses and reduces the output data rate on each bus, half the sample rate. The two converters are interleaved and used as a single 2 GSPS ADC.

The typical power consumption of the power-down mode converter is less than 3.5 MW and 128 pins, the enhanced thermal pad exposes the LQFP, and operates in industrial (-40°C ≤ _TA ≤ 85°C) temperature range.

Main specifications

apply

• Direct RF downconversion
• Digital oscilloscope
• Satellite set-top box
• Communication systems
• Test instruments