The HMC679LC3C is a T-trigger with integrated reset that supports clock frequencies up to 26 GHz. In normal operation, if the reset pin is not set, the output switches to the previous state on the positive edge of the clock. This creates a divide-by-two function at the clock input. Asserting the reset pin forces the Q output low, regardless of the clock edge state (asynchronous reset bit). Inverting the clock input supports negative edge triggering applications.
The HMC679LC3C also provides an output level control pin, VR, to compensate for losses and can also be used for signal level optimization. All signals entering the HMC679LC3C are terminated to on-chip ground at 50 Ω and can be AC- or DC-coupled. The output can be directly connected to a 50 Ω terminated system, while DC blocking capacitors can be used if 50 Ω terminated to a non-grounded DC voltage. The HMC679LC3C operates from a single -3.3V DC supply and is available in a RoHS-compatible 3x3 mm SMT ceramic package.
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- Serial data transmission up to 26 Gbps
- High-speed divider (up to 26 GHz)
- Broadband test and measurement
- RF ATE applications