- Exceeds LV and HV CPRI voltage and jitter requirements
- 2457.6, 1228.8 and 614.4 Mbps operation
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Integrated Delay Calibration Measurement (DCM) directly measures delays at T14 and toffset ≤ ± 800 PS
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DCM also measures chips and other delays ≤ PS accuracy± 1200
- Deterministic chip latency
- Independent transmit and receive seamless RE genlock loops
- Low noise recovery clock output
- Application cleaning without jitter and single hops
- > 8 kV ESD to CML IO, all other pins > 7 kV, > 2 kV CDM
- Hot-swap protection
- LOS, LOF, 8B/10B line code violations, commas and receiver PLL lock reports
- Programmable hyperframe length and the start of hyperframe characters
- Programmable transmit de-emphasis and receive with on-chip termination equalization
- Advanced testability features
- IEEE 1149.1 and 1149.6
- Generator/checker in high-speed BIST mode
- Multi-loop mode
- 1.8V or 3.3V compatible with parallel bus interface
- The 100-pin TQFP package exposes DAP
- Industrial - 40 to +85 ° C temperature range
illustrate
The SCAN25100 is a high-speed bidirectional serial data of 2457.6, 1228.8 and 614.4 Mbps on the backplane of an FR-4 printed circuit board, balanced cable, fiber optic transmission serializer/deseralizer (SerDes). The SCAN25100's integrated high-precision delay calibration measurement (DCM) circuitry measures better accuracy of the link delay element than ± 800 ps.
The SCAN25100 features separate transmit and receive system phase-locked loops, on-chip oscillators, and intelligent clock management circuitry that automates remote radio head synchronization, reducing the cost and complexity of external clock networks.
Although an SCAN25100 is MDIO interface programmed as well as via pin, it has configurable transmit de-emphasis, receive equalization, high rate selection, internal pattern generation/verification, and loopback modes. In addition to the SCAN25100 at high-speed BIST includes IEEE 1149.1 and 1149.6 testability.
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