DS90C383BMTX

• Product Introduction

peculiarity

所需的时钟/数据/ PD引脚之间没有特殊的启动顺序。 可应用于输入信号（时钟和数据），之前或之后的设备供电。
支持扩频时钟高达100kHz的频率调制和± 2.5％的中心扩散或-5％的偏差，向下蔓延。
“输入时钟检测”功能，将拉动所有LVDS对逻辑低电平时，输入时钟丢失和/ PD引脚为逻辑高电平时。
18日至68 MHz的移位时钟支持
中最佳的类设置及保持TxINPUTs时报
发射功率消耗 不到的BiCMOS替代40％的功率耗散
TX掉电模式 支持VGA，SVGA，XGA和双像素的SXGA。
窄总线减少了电缆的尺寸和成本
高达1.8 Gbps的吞吐量
高达227兆字节/秒的带宽
345毫伏（典型值）摆动LVDS器件的低EMI
PLL无需外部元件
TIA/EIA-644 LVDS标准的兼容
薄型56引脚TSSOP封装
改进：SN75LVDS83，DS90C383A更换

illustrate

CMOS/TTL data DS90C383B transmitter to 4 LVDS (Low Voltage Differential Signaling) data streams is converted to 28 bits. A phase-locked send clock is the parallel data streaming of more than one-fifth of the LVDS links. For each transmit clock cycle, 28-bit input data is sampled and transmitted. Transmit clock frequencies at 65 MHz, 24-bit RGB data and 3-bit LCD timing and control data (FPLINE, FPFRAME, DRDY) at 455 Mbps per LVDS data channel speed. It uses a 65 MHz clock and has a data throughput of 227 MB/s. DS90C383B emitters can be programmed to strobe along the rising edge or strobe at the falling edge through a dedicated pin. A rising-edge or fall-edge strobe transmitter will have a fall-edge strobe receiver without any conversion logic (DS90CF386) for interoperability.

This chipset is an ideal means to solve problems related to EMI and wide-cable, high-speed TTL interfaces.