peculiarity
> switching frequency of 400 Mbps (200 MHz).
0.1 ns channel-to-channel skew (typical)
0.1 NS Differential Offset (Typical)
3.3 ns maximum propagation delay
3.3V power supply design
LVDS input power drops high impedance
Low-power design (40mW@3.3V static)
Compatible with existing 5V LVDS networks
Accepts VID with a small swing (350 mV typical).
Open, short, and termination inputs support fail-safe
Compatible with ANSI/TIA/EIA-644
Industrial grade temperature. Scope of business (-40 °C to +85 °C)
Available in SOIC and TSSOP packages
illustrate
DS90LV032A is a quad CMOS differential line receiver designed for applications that require ultra-low power consumption and high data rates. The device is designed to support data transfer rates in excess of 400 Mbps utilizing low-voltage differential signaling (LVDS) technology (200 MHz).
DS90LV032A accept low-voltage (350 mV typical) differential input signals and convert them to 3V CMOS output levels. Receiver, supports three-state function, can be used for multiple outputs. The receiver also supports open-circuit, short-circuit, and termination (100Ω) input fail-safe. The output of the receiver will be all fail-safe conditions.
DS90LV032A and companion LVDS line drivers (such as DS90LV031A) high-power PECL/ECL devices are used as points, providing a new alternative for point-to-high-speed interface applications.