peculiarity
> 400 Mbps (200 MHz) switching frequency
0.1 ns channel-to-channel skew (typical)
0.1 NS DIFFERENTIAL OFFSET (TYPICAL)
Maximum propagation delay of 3.3 ns
3.3V power supply design
LVDS input power drops high impedance
Low Power Design (40mW@3.3V Static)
Available with existing 5V LVDS networks
Accept VIDs with small swings (350 mV typical).
Open, short, and stop inputs support fail-safe
Compatible with ANSI/TIA/EIA-644
Industrial temperature. Business scope (-40 °C to +85 °C)
Available in SOIC and TSSOP packages
illustrate
The DS90LV032A is designed for applications requiring ultra-low power consumption and high data rates for quad CMOS differential line receivers. The device is designed to support data rates in excess of 400 Mbps utilizing Low Voltage Differential Signaling (LVDS) technology (200 MHz).
The DS90LV032A accepts low-voltage (350 mV typical) differential input signals and converts them to a 3V CMOS output level. Receiver with tri-state capability for multiple outputs. The receiver also supports open, short, and stop (100Ω) input fail-safe. The output of the receiver will be fail-safe conditions.
The DS90LV032A and companion LVDS line drivers such as the DS90LV031A provide a new alternative to point-to-point high-speed interface applications.