peculiarity
Shift clock support from 20 to 65 MHz
Programmable Transmitter (DS90C383) Strobe Selection (Rising or Falling Edge Strobe)
Single 3.3V power supply
Chipset (TX + RX) power consumptionPower-down mode (Preparation of a single pixel per clock for XGA (1024 × 768).
Supports VGA, SVGA, XGA and higher addressability.
Up to 227 megabytes per second bandwidth
Up to 1.8 Gbps throughput
The narrow bus reduces the size and cost of the cable
The 290 mV swing LVDS device has low EMI
The PLL requires no external components
Low profile 56-pin TSSOP package.
Also available in a 64-ball, 0.8mm fine pitch ball grid array (FBGA) package
Falling edge data gating receiver
Compatible with the TIA/EIA-644 LVDS standard
> 7 kV ESD rating.
Operating temperature: -40°C to +85°C
illustrate
The DS90C383 transmitter converts 28-bit LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is more than one-fifth of the parallel traffic transmission of the LVDS link. Each transmit clock cycle, 28-bit input data is sampled and transmitted. The LVDS data stream of the DS90CF384 receiver is converted to 28-bit LVCMOS/LVTTL data. TRANSMITTING CLOCK FREQUENCY AT 65 MEGAHERTZ, 24-BIT RGB DATA AND 3-BIT LCD TIMING AND CONTROL DATA (FPLINE, FPFRAME, DRDY) AT A SPEED OF 455 MBS PER LVDS DATA CHANNEL. With a 65 MHz clock, the data throughput is 227 MB/s. The transmitter provides programmable edge data gating, convenient interface, and a variety of graphics controllers. The transmitter can be programmed to strobe on the rising edge or strobe on the falling edge, through a dedicated pin. The rising edge transmitter interop conversion logic does not have any falling edge receiver (DS90CF384). The devices are also available in a 64-ball, 0.8mm fine-pitch ball grid array (FBGA) package with 44% less PCB area than the TSSOP package.
This chipset is an ideal solution to issues related to EMI and cable size wide, high-speed TTL interfaces.