features
> 400 megabits per second (200 MHz) switching rate
channel-to-channel 0.1 ns (typical).
Typical skew (0.1 ns) differentiation
330 ns maximum propagation delay
3.3V power supply design
High impedance input in LVDS power drop
Low Power Design (40mW @ 3.3V Static)
Networks interoperable with existing 5V LVDS
Accept small rotary type (350) mV typical
Supports open, short, terminate input power outages
Compatible with the National Organization for Standardization (ANSI)/TIA/EIA-644
Industrial temp. - 40°C operating range (+85°C),
Available in SOIC and TSSOP packaging
description
This is a four DS90LV032A CMOS differential line receiver designed for applications that require ultra-low power consumption and high data rates. The device is designed to support data rates in excess of 400 megabits per second (200 MHz) utilizing low-voltage differential signaling (LVDS) technology.
DS90LV032A accept low-voltage (350 mV typical) differential input signals and convert them to CMOS output levels. The 3V receiver's tri-state capability supports one multiplexed output. The receiver also supports openness, VAT is changed from production to consumption, and the input power outage is terminated (100Ω). Output high receiver for all fault tolerance conditions.
With companion DS90LV032A LVDS line drivers (e.g. DS90LV031A) Provides a new alternative to high-speed point-to-point interfaces for high-power PECL devices/emitter coupled logic circuit element applications.