features
> 400 million bits per second (200 MHz) exchange rate
Channel-to-channel tilt of 0.1 ns (typical).
Typical tilt (0.1 ns) differential
330 ns maximum propagation delay
3.3V power supply design
High impedance input in LVDS power drop
Low Power Design (40mW @ 3.3V Quiescent)
Interoperable network with existing 5V LVDS
Accept the small swing (350) "mV typical
Supports open, short, terminating input blackouts
Compatible with the National Organization for Standardization (ANSI)/TIA/EIA-644
Industrial temp. - operating range of 40 ° C (+85 ° C),
Available in SOIC and TSSOP packaging
description
This is a quad DS90LV032A CMOS differential line receiver designed for applications requiring ultra-low power consumption and high data rates. The device is designed to support data rates in excess of 400 megabits per second (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.
The DS90LV032A accepts low-voltage (350 mV typical) differential input signals and converts them to CMOS output levels. Tri-state capability for 3V receivers with one output that can be used for multiplexing. Recipients also support openness, VAT is changed from production to consumption, and (100Ω) input blackouts are terminated. Output the high receiver to all fault-tolerant conditions.
With companion DS90LV032A LVDS line drivers (e.g. DS90LV031A) provides a new alternative to high-power PECL devices/emitter-coupled logic components for high-speed point-to-point interfaces.